1. Technical Field
This patent relates, in general, to a method of programming a flash memory device and, more particularly, to a method of programming a flash memory device, in which threshold voltage distributions of a cell connected to the last word line can be controlled to have a narrow width.
2. Discussion of Related Art
In recent years, there is an increasing demand for semiconductor memory devices which can be electrically programmed and erased and does not require a refresh function of rewriting data at regular intervals. Furthermore, to develop memory devices with a large capacity capable of storing lots of data, a high-integrated technique of memory cells has been developed. To increase the integration of the memory cells, a NAND flash memory device in which a plurality of cells are connected in series to form one string and two strings share one contact has been developed.
The NAND flash memory device includes a plurality of cell blocks and a plurality of circuits for driving the cells. Each of the cell blocks includes a plurality of cell strings. FIG. 1 is a circuit diagram for illustrating a portion of a construction including a cell string.
Each of cell strings 101 and 102 includes a plurality of cells for storing data, which are connected in series. A drain select transistor 110 and a source select transistor 120 are formed between the cell strings 101 and 102 and a drain, and the cell strings 101 and 102 and a source, respectively. Furthermore, cells are connected to word lines WL0 to WL31. The drain select transistor 110 and the source select transistor 120 are connected to a drain select line DSL and a source select line SSL, respectively. The number of each of the cell strings 101 and 102 is the same as that of bit lines BL. Accordingly, the number of the drain select transistors 110 and the source select transistors 120 is also the same as that of bit lines BL.
Meanwhile, each cell includes a gate in which a tunnel oxide layer, a floating gate, a dielectric layer, and a control gate are laminated on a predetermined region of a semiconductor substrate. The cell also includes a junction region disposed at both sides of a gate.
In the NAND flash memory device constructed above, program and erase are performed by controlling a threshold voltage of the memory cell while injecting and discharging electrons into and from the floating gate by means of F-N tunneling. For example, in order to program a selected cell, a program voltage is applied to a selected word line WL using an ISPP method, a pass voltage of about 10 V is applied to an unselected word line WL, a ground voltage Vss is applied to a selected bit line BL, and a power supply voltage Vcc is applied to an unselected bit line BL. At this time, the drain select line DSL is applied with the power supply voltage Vcc, the source select line SSL is applied with the ground voltage Vss, the common source line CSL is applied with the power supply voltage Vcc, and a P well is applied with the ground voltage Vss.
Meanwhile, in the erase operation, electrons injected into the floating gate are removed by applying an erase voltage of about 20 V to a triple P well and 0 V to the entire word lines of a selected block. In this case, electrons are injected into the floating gate of a programmed cell. Accordingly, the programmed cell has a positive threshold voltage. To the contrary, electrons are discharged from the floating gate of an erased cell. Accordingly, the erased cell has a negative threshold voltage.
However, the performance of a device depending on an over-program problem and read margin depends on the distributions of threshold voltages of a program cell of a NAND flash memory device. The threshold voltage distributions of the program cell are controlled by applying a program voltage using the ISPP method. The cell threshold voltage distributions are a very important factor in a multi-level cell.
However, if program is performed using the ISPP method, the distributions of the cell threshold voltages can be controlled to a narrow width, but there occurs a difference in the cell threshold voltage within the cell string on a cell basis. This is caused by a Back Pattern Dependency (BPD) phenomenon and an interference phenomenon, but is not related to the characteristics inherent in the string cell. More particularly, cells connected to the word lines WL0 to WL30 from the source select line and cells connected to the word line WL 31 adjacent to the drain select line have a slight difference in the threshold voltage.
FIG. 2 is a graph showing the distributions of cell threshold voltages when the ISPP method is performed on a NAND flash memory device of 1 MB. In FIG. 2, “A” denotes threshold voltage distributions of a cell connected to the first word line WL0, “B” denotes threshold voltage distributions of a cell connected to the second word line WL1, “C” denotes threshold voltage distributions of a cell connected to the last word line WL31, and “D” denotes threshold voltage distributions of cells connected to word lines from the first word line WL0 to the last word line WL31.
As shown in FIG. 2, the cell connected to the last word line W31, which is programmed lastly, is not influenced by a threshold voltage distortion phenomenon of an access cell depending on threshold voltages of neighboring cells (i.e., an interference phenomenon), but has an initial cell threshold voltage. Accordingly, the cell decides the left cell distributions of cell threshold voltage distributions of a chip. A difference in the distributions is about 0.3 V in a single level cell and about 0.15 V in a multi-level cell.
The cell threshold voltage that is distributed widely as described above degrades the read margin of the single level cell or the multi-level cell and has a bad effect on the reliability of a device, such as a cycling characteristic and a retention characteristic.